GPU Physical Verification Design Engineer, Cambridge

Do you love creating elegant solutions to highly complex challenges? Do you intrinsically see the importance in every detail? As part of our Silicon Technologies group, you'll help design and manufacture our next-generation, high-performance, power-efficient GPU. You'll ensure Apple products and services can seamlessly and expertly handle the tasks that make them beloved by millions. Joining this group means you'll be crafting and building the technology that fuels Apple's devices. Together, we enable our customers to do all the things they love with their devices. This role requires a mix of strategic engineering along with hands-on, technical work. You will be realizing the complete physical design verification closure from early design planning to tapeout. You will have hands on experience in physical design and large chip integration. Join us!

As a GPU Physical Verification engineer, you will work closely with the Physical Design team to drive physical verification aspects in the design cycle. You will work with physical design team, as you drive methodologies and"best known methods"to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support. You will manage and resolve design and flow issues related to physical design, identify potential solutions and drive execution. You will need to communicate and drive the needs of Physical Design Verification with cross-functional teams that will enable achieving the goals of the back-end design for the project.

Experience with hierarchical design approach, top-down design, budgeting, and physical convergence.\nExperience with Physical Verification checks including Base/Metal DRC, ERC, LVS, Process ANT, PERC, and ESD.\nExperience with P&R flows and Physical Verification tools (e.g. Calibre).\nGraduate os BS/MS and PDV relevant experience.

Experience integrating IP from both internal and external vendors and be able to specify and drive IP requirements in the physical domain.\nExperience with Physical Design topics: multiple voltage and clock domains, ESD solutions, and mixed signal block integration.\nExperience with large subsystem designs (>20M gates) with frequencies in excess of 1GHz applying brand new technologies.\nFamiliar with various process related design issues including Design for Yield and Manufacturability, multi Vt strategies and thermal Mgt.\nProven track record in solving complex PD and cross functional problems, driving results directly and or directing a team of engineers to innovate and execute on world class designs.\nUnderstanding of GPU architecture and design units.\nExperience with Floorplanning tools, P&R flows, global timing verification and Physical Design Verification Flows is required.