Senior CPU RTL Design Engineer - RISC-V Core Architect, Cambridge

SiFive UK Ltd. is seeking a skilled CPU Designer in Cambridge to architect, design, and implement new features in RISC-V CPU core generators using Chisel. This role requires a strong background in RTL design, collaboration with verification and physical implementation teams, and an emphasis on high-quality design.

The ideal candidate will have a BS/MS degree, relevant experience, and a strong understanding of current hardware design principles. Join us in a collaborative environment focused on innovation and excellence.